This invention generally relates to the field of electrostatic discharge (ESD) protection circuitry and, more specifically, improvements for silicon controlled rectifier (SCR) and NMOS circuits in the protection circuitry of an integrated circuit (IC).
The ongoing advancements in integrated circuit (IC) technologies have led to the use of lower supply voltages to operate the IC""s. Lower supply voltages help cope with a problem of hot carrier induced, limited lifetime for the IC""s. Designing IC""s with lower supply voltages requires the use of very thin gate oxides. The thickness of the gate oxides influences the amount of drive current that is generated. The thinner the gate oxide layer, the more drive current is generated, which thereby increases the speed of the circuit. The gate oxides (e.g., silicon dioxide) may have a thickness of less than 3 nanometers, and further advancements will allow the gate oxide thickness to scale down even further. The lower supply voltages also allow the use of silicon controlled rectifiers (SCRs) with very low holding voltages (e.g., 1.5-2.0V) without introducing a risk of latch-up. The thin gate oxides, which are used in conjunction with low supply voltages, require extreme limitation of transient voltages during an ESD event.
A problem arises using the very thin gate oxides because the oxide breakdown voltage is less than the junction breakdown voltage (e.g., 6-9 volts) that triggers an ESD protection circuit, such as an SCR or NMOS device. For example, a grounded-gate SCR (GGSCR) may be used to provide ESD protection for an (I/O) pad. The GGSCR has a junction breakdown voltage between 6-9 volts, which provides the trigger current for the SCR. As advances in technology allow reduction of the thickness of the oxide thickness below 3 nanometers, the gate oxide is subject to damage at turn-on and high current clamping voltages greater than approximately 4-6 volts.
Therefore, there is a need in the art for an ESD protection device having a lower trigger voltage, as well as a lower holding and clamping voltage that can protect the gate oxide from damage during turn-on and operation.
The disadvantages heretofore associated with the prior art are overcome by various embodiments of an electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry. In one embodiment, the ESD protection circuit comprises a pad, adapted for connection to a protected circuit node of the IC and an ESD protection device, coupled between the pad and ground. A diode turn-on device is coupled in a forward conduction direction from the pad to a first gate of the ESD protection device.
In a second embodiment, an ESD protection circuit in a semiconductor IC having protected circuitry and a plurality of mixed supply voltage lines, comprises an SCR having an anode coupled to a first voltage supply line and a cathode coupled to ground. Parasitic capacitance couples each voltage supply line to the grounded cathode. Optionally, at least one holding diode is coupled in a forward conductive direction from the first voltage supply line to the anode of the SCR. Optionally, at least one trigger diode is coupled in a forward conductive direction from the second trigger gate to a second voltage supply line.
As is discussed below, these two embodiments, as well as other various embodiments, provide ESD protection for the protected circuitry of an IC, such that the diode turn-on device provides a lower trigger voltage, as well as a lower holding and clamping voltage, which can protect the gate oxide from damage during turn-on and operation in the ESD event.